1. Field of the Invention
The embodiments of invention relate to the automation of the design and manufacturing of electronic systems, more particularly to the method and system for specifying system level constraints in a cross-fabric design environment.
2. Discussion of the Related Art
In general, an electronic system include a plurality of integrated circuit chips (IC) for performing various electronic functions. Each IC includes many electronic components (e.g. transistors, diodes, capacitors, inverters, logic gates, multiplexers, etc.) interconnected in a prescribed manner to respond to input electrical signals and produce other electrical signals according to the desired electronic function performed by the IC. For example, basic electrical components can be combined to form a larger scale component functioning as a memory cell, a multiplexer, or an arithmetic and logic unit (ALU). The various electronic components within the IC are interconnected with layers of wires made, for example, of metal and/or polysilicon.
FIG. 1 is a block diagram illustrating the interconnection of electronic components through multiple fabrics in accordance with the related art. Referring to FIG. 1, an electronic system includes one or more IC or die 140, one or more package 160 and one or more board, such as a printed circuit board (PCB) 180. Electrical signals into and out of the die 140 propagate through a plurality of pins or contact points 122 in a plurality of die buffers 120. The die 140 constitutes a first fabric for interconnecting the die buffers 120 from one IC die 140 to another IC die or other modules in the electronic system.
The die 140 is attached to a package 160, such as a ball grid array (BGA). A simple system may incorporate a single die 140 on a ball grid array (BGA) package 160. More complex system may involve multichip modules. The package 160 constitutes a second fabric through which a first buffer 120 or a module from a first die 140 is interconnected with a second buffer 120 from a second die 140 for exchanging electrical signals to be processed by the interconnected dies 140.
Conducting die bumps balls 142 are provided between the die 140 and the package 160 as electrical contacts between the die 140 and the package 160. Electrical signals from the die buffer 120 propagate through an interconnect 145 to the die bump 142. Similarly, electrical signal propagates from die bump 142 to package ball 162 through interconnect 165.
Multiple packages 160 can be attached to a PCB 180 to form a complex electronic system. These packages are routed through the PCB.
Referring to FIG. 1, a net include a first interconnect 145 for transmitting electrical signals between pin 122 of a die buffer 120 through a die 140 to a die bump 142, and a second interconnect 165 for transmitting electrical signals from the die bump 142 through the package 160 to a PCB 180 via package balls 142 and connectors 162. Thus, an electrical signal from the first die 140 on the first package 160 to a second die 140 on a second package 160 may propagate via a first net connecting the pins of the first die buffers 120 in the first die 140 through corresponding pins on the first package 160 to a first corresponding input or output pin located on the PCB 180 and via a second net connecting a second pin or connector on the PCB 180 through corresponding pins on the second package 160 to the pins of the second die 140.
A plurality of the die bumps 142 from the die 140 may be grouped to form an interface, i.e., electrical signals that are related to each other and to the function performed by the die 140. For example, the die 140 can be part of a memory module, e.g., a dual-inline memory module (DIMM). Then, a plurality of the pins 142 from the die 140 transmits digital data according to a double data rate (DDR2 or DDR3) standard. In another example, the plurality of the pins 142 from the die 140 forms a PCI express interface for communicating electrical signals to peripheral components on a computer bus in accordance to the PCI Express specification.
FIG. 2 is block diagram illustrating interconnection of interfaces across multiple fabrics. Referring to FIG. 2, an electronic system includes a first fabric 141 having a plurality of connection points 143, a second fabric 161 having a plurality of connection points 163, and a third fabric 181 having a plurality of connection points 183. Each of the fabrics 141, 161 and 181 can be one of a die, a package, a board and a field programmable gate array (FPGA). Each of the connection points 143, 163, 183 can correspond to an input or output buffer in an IC, a bump in a die, a ball in a package, or a connector of a PCB.
In FIG. 2, an exemplary 7-connection interface traverses the first fabric 141 through a first group 150 of seven of the connection points 143 in the first fabric 141. The 7-connection interface traverses the second fabric 161 through a second group 170 of seven of the connection points 163 in the second fabric 161. The 7-connection interface traverses the third fabric 181 through a third group 190 of seven of the connection points 183 in the third fabric 181. As shown in FIG. 2, the location of the connection points 143 in the first group 150 within the first fabric 141 may be different from the location of the corresponding connection points 163 in the second group 170 within the second fabric 161 and from the location of the corresponding connection points 183 in the third group 190 within the third fabric 181.
The number of connections in an interface is not limited to the exemplary number 7. The number of connections in each interface is selected based on the electrical signals to be carried through the interface. For example, an interface for transmitting bus signals in a 32-bit computer system may require 32 connections. Moreover, the number of connection points for an interface may differ across fabrics depending on design and signal requirements. For example, a 32-bit interface on a package may have 16 connection to a first die and remaining 16 connection points to a second die.
An interface net interconnects a connection point 143 from the first group 150 in the first fabric 141 through a corresponding connection point from the second group 170 in the second fabric 161 via an interconnect 145, to a corresponding connection point 183 from the third group 290 in the third fabric 181 via an interconnect 165.
Electronic systems are becoming more and more complex with many dies 140 to be positioned on a package 160, and several packages to be attached to a PCB 180. The number of interfaces and corresponding nets to be accommodated increases with the high pin count designs and the multiplicity of layers in flip-chip packaging. One of the challenges in designing such complex electronic systems is to assign an interface to corresponding groups 150, 170 and 190 of connection points across the respective fabrics 141, 161 and 181 and to assign each net of the interface to the corresponding connection points 143, 163 and 183 from the respective groups 150, 170 and 190 in the respective fabrics 141, 161 and 181.
The design of such complex electronic systems requires using a computer processing system having one or more electronic design automation application software that provides computer-based tools specifying the desired characteristics of an electronic circuit, enter circuit components to create the desired electronic circuit, interconnect the circuit components to achieve some desired logic or function, and converting the logical interconnection of the components into a layout that represents the different materials and devices that constitute the electronic circuit using geometric shapes.
The design of the electrical system shown in FIG. 2 on a computer system can be partitioned among several teams of designers to accommodate the need to reduce time to market for the product being designed and leverage the expertise of each domain. In a vertical partitioning scenario, each of the fabrics 141, 161 and 181 can be designed by a separate team of designers. For example, an IC design team can generate the placement of the die bumps 142 for IC 140. A package design team can optimize the location of the package balls 162 for interconnecting the die 140 to the package 160 and for interconnecting the package 160 with the PCB 180. A PCB design team can optimize the locations of the package balls 162 on the PCB 180.
In the related art, the PCB design may include the integration of one or more field programmable gate arrays on the PCB along with non-FPGA components to be connected to the one or more FPGA. The pin assignment is typically based on a spreadsheet. The PCB design team will generally perform pin assignment without taking into consideration the placement of the other components and the routing of the interfaces and signals on the PCB.
In the related art, the pin assignment for the FPGA and other IC modules is done manually and pin-by-pin without consideration for how the placement of the FPGA and the other IC modules might affect or be affected by the placement and routing of other components on the PCB. A design project that is unaware of the impact of other PCB components on the overall placement and routing might lead to suboptimal pin assignment resulting in an increase in the number of layers on a PCB design. Moreover, the related art approach to the electronic design project may lead to unnecessary iterations at the tail end of the design cycle because the IC design, package design and PCB design teams have to make several iterations to tweak the pin assignment in their respective fabrics.
Hence, the PCB layout designer and the package designer go back-and-forth through an increased number of iterations until the PCB layout obtains an acceptable routing of the signals from the package pins on the available layers on the PCB. The PCB designer may propose pin swapping to improve routability. Any change in the pin assignment by the package designer or the PCB designer will cause a new iteration because the schematic design has to be changed to reflect the change in pin assignment. Accordingly, the design cycle might increase by days or even weeks to account for each such iterations.